As the technology node scales down to 45nm and beyond, the significant increase in design complexity and cost propels the globalization of the $400-billion semiconductor industry. However, such globalization comes at a cost. Although it has helped to reduce the overall cost by the worldwide distribution of integrated circuit (IC) design, fabrication, and deployment, it also introduces ever-increasing intellectual property (IP) privacy and integrity infringement. Recently, primary violations, including hardware Trojan, reverse engineering, and fault attack, have been reported by leading semiconductor companies and resulted in billions of dollars loss annually. While hardware IP protection strategies are highly demanded, the re- searches were just initiated lately and still remain preliminary. Firstly, the lack of the mathematical abstractions for these IP violations makes it difficult to formally evaluate and guarantee the effectiveness of the protections. Secondly, the poor scalability and cost-effectiveness of the state-of-the-art protection strategies make them impractical for real-world applications. Moreover, the absence of a holistic IP protection further diminishes the chance to address these highly correlated IP violations which exploit physical clues throughout the whole IC design flow. The dissertation proposes a synergistic framework to help IP vendors to protect hardware IP privacy and integrity from design, optimization, and evaluation perspectives. The proposed framework consists of five interacting components that directly target at the primary IP violations. First, to prevent the insertion of the hardware Trojan, a split manufacturing strategy is proposed that achieves formal security guarantee while minimizes the introduced overhead. Then, to hinder reverse engineering, a fast security evaluation algorithm and a provably secure IC camouflaging strategy are proposed. Meanwhile, to impede the fault attacks, a new security primitive, named as public physical unclonable function (PPUF), is designed as an alternative to the existing cryptographic modules. A novel cross-level fault attack evaluation procedure also is proposed to help designers to identify security-critical components to protect general purpose processors and compare different security enhancement strategies against the fault attack. All the five algorithms are developed based on rigorous mathematical modeling for primary IP violations and focus on different stages of IC design, which can be combined synergistically to provide a formal security guarantee.